A 2GHz, 17% tuning range quadrature CMOS VCO with high figure–of–merit and 0.6° phase error

This paper presents a quadrature VCO implemented in a standard 0.35µm CMOS process. The VCO draws 16mA from a 1.3V power supply, can be tuned between 1.91 GHz and 2.27GHz, and displays a phase noise of -140dBc/Hz or less at 3MHz offset frequency from the carrier, for a minimum phase-noise figure-of-merit of 184 dB. The maximum departure from quadrature between the VCO phases is 0.6°

A time-variant analysis of the 1/f^(2) phase noise in CMOS parallel LC-Tank quadrature oscillators

This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis

Comparison of the Image Rejection between the Passive and the Gilbert Mixer

This paper presents a comparison of the image rejection between Gilbert mixer and the passive mixer. A simple model for mixers is set up, and the image rejection performance of passive and Gilbert mixer is analyzed based on it. Simulations and calculations were done to compare the image rejection of the two mixers. The results show that the Gilbert mixer, comparing with the passive one, shows a stronger rejection to the amplitude error of the quadrature signals at its input

More on the 1/f(2) phase noise performance of CMOS differential-pair LC-tank oscillators

This paper presents a rigorous phase noise analysis in the 1/f2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of -144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theor

A 1.8 GHz CMOS VCO with reduced phase noise

A 2 V, 6 mA, 15% tuning range, 1.8 GHz VCO implemented in a standard 0.35 μm CMOS process is presented. The phase noise of the VCO has been greatly reduced by means of on-chip filters and one off-chip low frequency inductor. The phase noise measured at 3 MHz offset from the carrier is between -141.5 dBc/Hz and -138.5 dBc/Hz over the whole tuning rang

Efficient performance simulation of class D amplifier output stages

Straightforward simulation of amplifier distortion involves transient simulation of operation on a sine wave input signal, and a subsequent FFT of the output voltage. This approach is very slow on class D amplifiers, since the switching behavior forces simulation time steps that are many orders of magnitude smaller than the duration of one period of an audio sine wave. This work presents a method of simulating the amplifier transfer characteristic using a minimum amount of simulation time, and then deriving THD from the results

Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop

This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 ¿m BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz

45% power saving in a 0.25μm BiCMOS 10Gb/s 50Ω-terminated packaged active-load laser driver

A 0.25mum BiCMOS laser driver based on active loads allows operation at 10Gb/s while drawing 5mA from a 1.8V supply. The design guarantees the correct matching of the driver outputs without the use of physical 50Omega load resistors. This enables a theoretical current consumption reduction of 50% (45% in the actual prototype) compared to the traditional laser-driver design